The present invention relates to computer memory, and more specifically, verifying memory array repairs.
Testing and repairing of memory arrays prior to release to a customer is a common practice during memory array or integrated circuit fabrication. Integrated circuits (ICs) may include embedded memory arrays such as an embedded dynamic random access memory (DRAM) array, which may require testing and repair. ICs are typically formed on wafers containing multiple ICs. For testing and other purposes, each IC may include an electronic chip identification number (ecid).
These embedded memory arrays are analyzed by the fabricator using a built-in-self-test (BIST) unit that is included on the IC or using separate, stand alone testing units. The test determines the memory cells within the memory that are defective.
An advanced feature of these arrays is the incorporation of extra memory capacity that can be configured on a bit-by-bit basis to replace failed array elements. Configuring this extra memory capacity allows for hardware that can repair around damaged arrays and can continue to function without replacement or degradation. The manner in which memory is repaired shall be referred to herein as a “repair algorithm.” Applying a repair algorithm rather than de-allocation may preserve portions of these caches that may have otherwise been de-allocated.